ACUGEN® Software can create a test for your FPGA or Large PLD designs on a fee-for-service basis. This helps customers who have too few designs to justify purchasing test generation software and it helps prospective customers see how well ACUGEN products perform on their designs.
A Service Run includes processing through our FPGA Preprocessors, the ATGEN® test generator,
and appropriate translation software for your tester, if necessary.
How It Works:
You send us a Purchase Order for the fee quoted and the specific input files for your design. We will generate the vectors and perform any translation necessary for your test environment. Average
turnaround time is five business days.
Please be sure to review your tester options and include any requirements, as well as a list of any
board imposed pin constraints if the application is an in-circuit board test.
Guidelines:
• If we get over 90% PINS fault coverage, we will return the test vectors.
• If we get under 90% PINS fault coverage and find a serious testability problem, we will return the SHARPEYE TM Testability Report plus the test vectors.
Examples of serious testability problems are:
- counter that is not loadable or breakable and is larger than 10 bits
- one-shot, where a single edge on one signal produces two or more edges on another signal
- memory that is not initializable to a reliable state in a fixed number of vectors
Purchase Order Processing:
Fees are as follows:
- JEDEC-based PLD's = one half of the Premium PC List Price
- FPGA's = one-fourth of the Premium PC List Price
- SHARPEYE Testability Analysis only = $500 per design
ATGEN and ACUGEN are registered trademarks and AAACT, AALCA, AAMAX, AALAT, AAQL, SHARPEYE & FASTpass are trademarks of ACUGEN Software, Inc. All other trademarks are the property of their respective holders.21apr96