ATGEN® software automatically generates high coverage functional test vectors for all types of Programmable Logic Devices (PLDs), including PALs®,FPLAs, FPGAs, FPLSs, and other architectures. These vectors are applied after programming, on a programmer or in-circuit board tester. Testing PLDs individually prior to functional board test or system test results in large savings in testing, diagnosis, repair, and inventory costs. This product is one of a family of ATG products for PLDs that meets the needs of electronic equipment manufacturers and their suppliers in all areas of PLD testing.
• No fixed limit- depends on host computer resources
• The most thorough tests for any size device
• Expedient: Critical-path backtrace technique for shallow circuitry
• Abstract: Effective on counters
• Goonly: Effective on circuits with internally generated clocks, sets and resets.
• Thorough: Effective on state machines
• See attached models library
• For optional device support, please refer to our JEDEC-based Device Models Price list.
• PLD programmers
• Component testers, translators available
• In-circuit board testers, translators available
• 1 year telephone support
• 1 year software updates
• 1 year crisis support -- if a problem PLD is holding up your manufacturing, we will analyze the design and vectors and make recommendations for resolving the problem.
• Functional, no preload
• Automatic race detection and repair
• Automatic conflict detection and repair on bidirectional pins
• Menu and fill-in-the-form interface
• Batch facility
• Comprehensive manual
• Generate equations from JEDEC file in pin-number format
• Utility to generate detected & non-detected fault lists
• Pinswapping utility to convert vectors between DIP & LCC pinouts
• Detection goal
• Time limit
• Maximum number of vectors
• Maximum burst size
• Use vectors from source JEDEC file?
• First vector # to use
• Mark unknown state with X, F, N
• Verbose print to screen?
• Clock format: non-return, return-to-zero, mixed
• Vector minimization: low, moderate, maximum
• Tri-state testing: none, pull-high, pull-low, midband
• Initialization, 4 options: unknown, powerup low, powerup high, seed vectors
• Possible detects optimally analyzed in fault simulator?
• Expect state reduction, 2 options: all cares, detects only
• Fault classes, 6 settings: pins, logic, logic+intact, logic+intact+blown, Mil454,
• Mil454+blown
• Bidirectional pins, 7 settings controlling transient and settled state I/O contention prevention
• Type of test, 6 settings: functional, functional+DC, functional+DC+AC, in-circuit board, device+board, custom details
• Pins constrained: tied high, low or together, or not fixtured. Output and bidirectional pins may be joined.
• FASTpass Mode achieves faster throughput if run time is critical
• Event-driven, time-based algorithms
• Concurrent fault simulation
• Fault classes: pins, logic, intact fuses, blown fuses
• Most up-to-date vector minimization
• Credit for original purchase price or current list price (whichever is less) towards higher priced products if Technical Support Service is current.
• 386 (or higher) MS-DOS or Windows NT PC with hard disk and parallel port; VAX/VMS; Alpha, Sun4, Solaris 1.0 &2.3, and SPARC running Sun OS; HP9000/700 running HP-UX
• Signed license, Parallel port key
• High software development rate -- small releases every 3-6 months, major releases every 6-12 months.
• Latest technology, active engineering
• For companies requiring more than one PC/DOS platform at one location for wither high volume throughput or the capability to run ACUGEN products simultaneously. The configuration includes:
• One set of product diskettes:identical products run on all machines
• A security device for each computer, linked together by six feet of cable
This configuration is not appropriate for companies that have test generation needs at multiple sites.
• Generate models for whole-board simulators, such as Teradyne’s LASAR6 and GenRad’s HILO. Translators to all popular device, board and AC testers (See separate translator document.)