Overview
PROMATG software automatically generates test vectors and predicts timing information for PROMs, EPROMs, and EEPROMs. This product, when used in conjunction with one of our AC translators, provides a complete testing solution for users who need AC, DC, and functional tests for PROMs, EPROMs, and EEPROMs. When this product is used in conjunction with one of our in-circuit board test translators, it provides a complete solution for users who need to verify the in-circuit functionality of PROMs, EPROMs, and EEPROMs.
Product Highlights
• Easy to use
• Uses standard device programmer file formats
• No debug required
• Users can create device models and timing files
• Supports component and in-circuit board testing applications
• Accurately predicts setup times and propagation delays
• Interfaces with all ACUGEN® translators
• Binary, gray code, and pseudo-random addressing sequences
Highly-Optimized Test Generation
The generated test vectors are organized to maximize test coverage and minimize ATE resources. Typically, fewer than 60 vectors are needed to explicitly observe pin stuck-at faults and pin state transitions. These vectors are placed in self-initializing vector sets at the front of the test pattern and provide excellent device coverage. In addition, a functional test pattern composed of a user-definable number of test vectors can be generated to perform partial cell verification using a binary, gray code, or pseudo-random addressing sequence.
For Component Test
PROMATG software writes test vectors and timing information to a JDL file that can be translated using one of our AC translators into a complete test program to verify devices for AC parametric, DC parametric, and functional compliance. Please see the translator status sheet and the translator product descriptions for more details.
The test generated for a component testing application can be customized as follows:
DC Parametric Test Pattern
• None
• Solid Ones and Zeroes
• Walking/Sliding Ones and Zeroes
• Gray Code addressing sequence
Functional Test Pattern
• Pseudo-Random addressing sequence
• Both Solid and Walking/Sliding
• Binary addressing sequence
For In-Circuit Board Test
PROMATG software writes test vectors to a JWV file that can be translated using one of our in-circuit board test translators into a complete test program to verify a device’s in-circuit functionality. Please see the translator status sheet and the translator product descriptions for more details.
The test generated for an in-circuit board testing application can be customized as follows:
Board Topology Constraints
• Tie High or Low
• No Drive or No Sense
• Off
• Pseudo-Random addressing sequence
• Force to any JEDEC state
Test Pattern
• Binary addressing sequence
• Gray Code addressing sequence
• Join
• User-definable burst size
Device Model and Timing File Support
PROMATG software includes over 100 device models and over 300 device timing files which support the most popular PROM, EPROM, and EEPROM devices. The user’s manual contains instructions on how to create additional device models and timing files.
Platforms Available
PROMATG software is available for IBM compatible PCs running PCDOS or MSDOS, Sun 3 workstations running SunOS 4.0.3 or later, Sun SPARCstations and Sun 4 workstations running SunOS 4.1.1 or later, and VAX/VMS.
Technical Support & Updates
Updates and technical support during the first year are included in the product purchase price, including bug fixes, enhancements to software and documentation, and telephone support.
Requirements
The PROMATG software is an option to the ATGEN® line of automatic test generators and must be run in conjunction with an ATGEN base product and one of the ACUGEN translators.