PROGBSDL software converts a BSDL file for an unprogrammed PLD into a BSDL file with the same pin usage as the programmed PLD.
Easy to Use
The program can be invoked in a menu mode or from the command line. Either way, the user provides the filename for the unprogrammed BSDL and the filename for the PLD design. These files are then processed and a customized BSDL file written out automatically, typically in about 1 minute.
Why Customize BSDLs?
The BSDL files obtained from the PLD vendor represent the unprogrammed device, and typically declare nearly all pins to be bidirectional. In an in-circuit board test or partial scan situation, many of these ‘bidirectional’ pins can only be used as inputs because they are on nets with another driver that cannot be disabled during the scan test. In other situations, there is no tester channel fixtured for this pin. In these cases, the best approach may be to modify the BSDL to declare these problem pins as inputs or unused.
Save One Hour Per Device!
Modifying BSDL files by hand is time consuming, tedious and error-prone. If an FPGA has 200 pins, with each pin requiring changes in three places in the BSDL, and each change consuming 5-10 keystrokes, the complete edit task could require 3000 to 6000 keystrokes. PROGBSDL software requires fewer than 100 keystrokes to accomplish the same task.
How Does PROGBSDL Software Work?
PROGBSDL software reads the PLD design files to determine how each pin is used in the design. A standard ACUGEN® ATGEN® constraint file (.acn) may be used to further restrict pin usage. The software makes the reasonable assumption that the pin usage in the PLD design is compatible with the board the PLD is installed on. Once the design-specific pin usage is determined, a new BSDL file is written with a modified boundary scan register description. Only the BSDL statements related to the EXTEST operation are changed.
Device Support
PROGBSDL software includes support in automatic mode for the following PLD Design file types: JEDEC (.JED file); Actel ACT 1, 2 & 3 (.PIN + .ADL files); Altera MAX & FLEX (.EDF/.EDO + .FIT files or .RPT + .FIT files); Lattice pLSI & ispLSI (.SIM files); Quicklogic pASIC (.EDF/.EDO files); XILINX LCAs 2000-9000 (.XNF files w/ -gut). In manual mode, it can work with any BSDL file.
User Control
PROGBSDL software provides two features for users wanting more control over BSDL customization without the burden of editing the BSDL file directly. A simple fill-in-the-form/ menu screen allows user control of the mapping rules used by the software. For further control, another form screen allows mapping control for individual pins.
Standards Compliance
BSDL files read by PROGBSDL software are checked against a large number of IEEE Std 1149.1b-1994 specification rules. Any BSDL files produced by this tool will be at least as conforming as the input BSDL file.
Configurations
This PROGBSDL product is part of the ACUTAP Toolkit. It can be licensed for stand-alone use or as an add-on to an ATGEN vector generator.
Requirements
The host computer must have 8 MB of RAM and 25 MB disk available for use by this program.
Host Computers
PROGBSDL software runs on x86/DOS, x86/Windows (3.1, 3.11, 95, NT), HP9000/700 series/HPUX, Sun SPARC/Solaris I, and SPARC/Solaris II computers.
Technical support
Technical support and updates are provided under the support agreement for your base product.
Please refer to the ACUTAP Toolkit product description for additional information.