JTS Plus is a software package that translates the output of ACUGEN AADELAY TM software (the .JDL file) into a FACTOR test program and .LMI file(s). When JTS Plus is used with ACUGEN ATG and AADELAY software, PLD test program development for the Fairchild Sentry tester is truly automated. JTS Plus is easy to use and will produce test programs that will verify PLDs for DC Parametric, Functional, and AC Parametric compliance at three test temperatures.
AC Parametric Testing
JTS Plus will automatically create AC parametric tests to verify a PLDs compliance with its tPLH, tPHL, tPLZ, tPHZ, tPZL, tPZH, tSU, and tPW (minimum clock pulse width) specifications. All AC tests are written using the FACTOR TTIME executive (binary search) for fast execution times. The end user can specify the number of propagation delay tests to perform on each output pin (60 maximum). All AC test limits are determined by the delay, phase, and settling time data obtained from the ACUGEN AADELAY .JDL file. The .JDL file data enables JTS Plus to create AC tests for PLD designs with aggregate delays, complex feedback paths, I/O switching, etc., as effortlessly as AC tests for simple PLD designs.
JTS Plus provides full software control over the AC test loads through the use of the performance board relays. Each AC test can have the output pins connected to a pull-up load, a pull-down load, both a pull-up and pull-down load, or no load. The pull-up and pull-down load voltages are fully programmable to support multiple PLD logic families (TTL, CMOS, ECL, etc.). A schematic of an AC performance/load board is included with JTS Plus.
JTS Plus will create the time-to-tri-state tests (tPLZ and tPHZ) to provide maximum timing edge search accuracy. These tests are written such that their timing threshold levels (S0 and S1) are a function of the PLD's actual loaded output voltage. The threshold level offsets, normally ±0.5V, are user-programmable.
JTS Plus creates FACTOR code to characterize a PLD's sensitivity to its supply voltage. The FACTOR SPLOT executive is used to perform VCC vs VIL, VCC vs VIH, VCC vs VOL, and VCC vs VOH shmoo plots. Each plot's start and end points are user-definable. The user may also select the plotting axis for each parameter. At run-time, the user can enable or disable the characterization plots through the SWITCH variable.
Fast DC Parametric Testing
All DC Parametric tests except VIL and VIH tests are performed using non-interpretive macros. Although these macros take longer to compile, device throughput is greatly enhanced at test time. Most PLDs can be completely tested in one to four seconds. The VIL and VIH tests are performed with the FACTOR VLS (Voltage Level Search) executive.
DC Parametric Test Sequencing Optimizer
JTS Plus will optimize all DC Parametric tests by finding the first local memory statement where all pins appear in the proper state for the test. For example, JTS Plus will choose the first local memory statement where all output pins are low to perform Vol tests. This saves times by not having to continuously cycle through .LMI files for each pin that needs to be tested. If the local memory statement occurs in a .LMI file that isn't a stand-alone module, JTS Plus will automatically sequence through the necessary .LMI file loads to place the PLD in the correct state.
The user can turn off the optimizer to handle problematic DC parametric test cases. For example, a DC parametric testing problem may occur when testing a PLD for input leakage current compliance. The PMU forcing voltage can "clock" a registered PLD into another state where the remaining pins to be tested change their I/O function (Input to Output). Subsequent testing will falsely indict these pins for excessive leakage current. With the optimizer is turned off, all DC Parametric tests will occur at the first local memory statement where a pin is in the proper state. After each test, the .LMI file will be cycled from the last initializable point to insure that the pin under test is in the proper state regardless of what may have transpired during previous DC tests.
Three Temperature Test Support
JTS Plus produces test programs that support force and limit conditions for three user-definable test temperatures. During testing, the any test temperature can be selected via a menu or by setting a global variable. Any DC Parametric, Functional, or AC Parametric test can be included or excluded at any test temperature.
JTS Plus produces test programs that can be run in one of four datalogging modes: 1. Abort on first fail, 2. Do all tests, 3. Read-and-record - aborting on first fail, and 4. Read-and-record all tests. Both VKT and line printer datalogs are possible. All DC Parametric, Functional, and AC Parametric tests are datalogged with descriptive headers. All Functional tests will include pass/fail information. All AC Parametric propagation delay test limits and results are descriptively referenced to the timing generator edge (Data Lead, Clock Lead, or Clock Trail) that caused the transition.
Multiple LMI File Support
JTS Plus will support translations that require up to 999 .LMI files (over 4 million vectors). JTS Plus will automatically sequence all .LMI files for functional testing at up to three different supply voltages. Each .LMI file contains a commented header section with the file's source and object file name and a file creation time and date stamp. The header will convey whether the .LMI file can be run as a stand-alone module. In cases where the .LMI file can't be run as a stand-alone module, JTS Plus produces a list of .LMI files that must be sequenced using an overlaying technique prior to loading and running the .LMI file. This information is listed for informational purposes only, as JTS Plus handles the .LMI file sequencing automatically. JTS Plus generates all dynamic register loads (LSETs) using only the primary registers for maximum system compatible. Any non-pipelined statements are avoided whenever possible. The only exception to this is a single LSET RZ statement which is placed at the beginning of each .LMI file. JTS Plus will optionally include each .JDL file test vector as a comment just prior to the local memory statements that were generated from it.
Full-Featured Software Pin Scrambler
JTS Plus has a full-featured software pin scrambler that enables the user to map the original JDL file's vector pin column sequence to their load board requirements. This lets the user test most PLDs on a single load board. Pin scrambling may also be used to map test vectors for different IC package styles, e.g., DIP, LCC, PLCC, and SOIC.
Test Programs Can Be Modified Easily
The test programs created by JTS Plus use variables for all force, sense, limits, etc. These variables are declared and assigned at the start of each program. If the user desires to change a value, only the variable assignment need be altered, which greatly simplifies test program modifications, quality control, and maintenance.
All test programs contain a commented reference header section which documents the FACTOR executive requirements, the load/performance board and DUT card requirements, the name of the JEDEC/.JWV/.JDL file used, the name of the pin mapping file used, the programmer's name, as well as several lines of user-supplied comments. The header also contains a DUT-to-Tester pin mapping diagram which details the function of each DUT pin and its tester resource requirements (DPS, load, etc.).
Unlimited PLD Support
JTS Plus comes standard with several parameter files for both commercial and military PLDs. These parameter files contain DC and AC parametric test conditions and limits. The user can use these files directly, modify the files to suit their needs, or create new parametric files using a text editor or SM, a menu driven, fill-in-the-blanks parameter file editor. JTS Plus comes with detailed instructions on how to create your own parameter files. JTS Plus is presently available for the following host platforms:
IBM PC/XT/AT personal computers and compatibles running the PCDOS or MSDOS operating system version 2.0 or later.
DEC VAX computers running the VMS operating system.
Technical Support Service and Updates
Technical support is provided under the support plan for your particular ATGEN® base product.