JTS is a software package that translates the output of ACUGEN ATGTM software (the JWV file) into a FACTOR test program and LMI file(s). When JTS is used with ACUGEN ATG software, PLD test program development for the Fairchild Sentinel or Sentry tester is truly automated. JTS is easy to use and will produce test programs that will check PLDs for DC Parametric and Functional compliance at three test temperatures.
Multiple LMI File Support
JTS will handle translations that require up to 999 LMI files (over 4 million vectors). JTS will automatically sequence all LMI files for functional testing at up to three different supply voltages. Each LMI file contains a header section with the file's source and object name. The header will also state whether or not the LMI file can be run as a stand-alone module. In cases where the LMI file can't be run as a stand-alone module, JTS produces a list of LMI files that must be sequenced using an overlaying technique prior to loading and running the LMI file. This information is listed for informational purposes only, as JTS handles the LMI file sequencing automatically. JTS generates all dynamic register loads (LSETs). Only the primary registers are used for maximum system compatible. Any non-pipelined statements are avoided whenever possible. The sole exception to this is a single LSET RZ statement which is placed at the beginning of each LMI file. JTS will optionally include each JWV file test vector as a comment just prior to the local memory statements that were generated from it.
Full-Featured Pin Scrambler
JTS has a full-featured pin scrambler that allows the user to map the original JWV file's vector pin column sequence to their load board requirements. This enables the user to test most PLDs on a single load board. Pin scrambling may also be used to map test vectors for different IC package styles, e.g., DIP, PLCC, and LCC.
Fast DC Parametric Testing
All DC Parametric tests are performed using non-interpretive macros. Although these macros take longer to compile, device throughput is greatly enhanced at test time. Most PLDs can be completely tested in one to two seconds.
DC Parametric Test Sequencing Optimizer
JTS will optimize all DC Parametric tests by finding the first local memory statement where all pins appear in the proper state for the test. For example, JTS will choose the first local memory statement where all output pins are low to perform Vol tests. This saves times by not having to continuously cycle through LMI files for each pin that needs to be tested. If the local memory statement occurs in a LMI file that isn't a stand-alone module, JTS will automatically sequence through the necessary LMI file loads, etc. to place the PLD in the correct state.
The user can turn off the optimizer to handle special test cases where an input current test "clocks" a registered PLD into the wrong state (input pins may no longer be inputs due to the clocking phenomena). When the optimizer is turned off, all DC Parametric tests will occur at the first local memory statement where a pin is in the proper state. After each test, the LMI file will be cycled from the last initializable point to insure that the pin under test is in the proper state regardless of what may have occurred during previous DC tests.
Three Temperature Test Support
JTS produces test programs that will test PLDs at up to three different test temperatures. The test temperature can be selected either though a menu or by setting a global variable. Any DC Parametric or Functional test can be excluded at any test temperature.
JTS produces test programs that can be run in one of four modes: 1. Abort on first fail, 2. Do all tests, 3. Read-and-record - aborting on first fail, and 4. Read-and-record all tests. Both VKT and line printer datalogs are possible. All DC Parametric and Functional tests are datalogged with descriptive headers. All Functional tests will include pass/fail information.
Test Programs Can Be Modified Easily
All test programs contain a header section which documents the translation process, tester requirements, load board and DUT card requirements, which JEDEC/JWV file was used, which pin mapping file was used, the programmer, as well as several lines of user-supplied comments.
All test programs use variables for all force, sense, limits, etc. These variables are declared and assigned at the start of each program. If the user desires to change a value, only the variable assignment need be altered, which greatly simplifies test program modifications.
Unlimited PLD Support
JTS comes standard with over fifty parameter files for both commercial and military PLDs. These parameter files contain the DC parametric test conditions and limits for the PLD. The user can modify these files to suit their needs or create new parametric files using a text editor. JTS comes with detailed instructions on how to create your own parameter files so the user should never be more than a few minutes away from obtaining support for any PLD device.
JTS is presently available for IBM PC/XT/AT personal computers and compatibles.