Product Description: JED2VCL

ACUGEN® .JWV File to HP3065/3070 .VCL File Translator

JED2VCL is a software utility that translates the output of ACUGEN Software's ATGEN® test generator (the .JWV file) into a .VCL (Vector Control Language) file for use with the HP3065 series In-circuit Program Generator (HP IPG-II) or the HP3070 series Integrated Program Generator (HP IPG) software package. When JED2VCL is used with ATGEN software, PLD test program development for Hewlett Packard's HP3065/HP3070/HP3075 family of board test systems is truly automated. JED2VCL is easy to use and will produce a complete .VCL file.

Undisplayed Graphic

Automatic VCL File Creation

No Debug Necessary

Easy To Use

JED2VCL produces the Declaration, Vector Definition, and Vector Execution sections of the .VCL file.

VCL Declaration Section

JED2VCL produces the Declaration section which declares the vector processor and test type. Pin assignments are made for power, ground, single pin, and multi-pin groups. After assignment, the single pin and multi-pin groups are declared as inputs, outputs, or bidirectional based on .JWV file's requirements. If a group is bidirectional, JED2VCL assumes that this device could be "busable" and creates "disable with" statements with pin states provided that the appropriate single vector disables exists in the .JWV file. If single vector disables aren't available, JED2VCL will create a commented Disable Section that contains an optimized disable vector list and then generate a "disable with" statement without pin states and a "warning" message. The "disable with" statement without pin states will cause IPG to assume that multiple disable vectors are required and it will generate information in the IPG Summary Report and IPG Details Report indicating that the disable vectors must be added. The user may then add the optimized disable vectors from the Disable Section to the Vector Definition sections of any busable devices that require them.

For those testers that support timing sets, a default timing set is generated. For those testers that don't support timing sets, the appropriate "vector cycle" and "receive delay" information is generated along with commented timing set information. If the PCF (Pattern Capture Format) option is enabled, JED2VCL will produce the necessary "pcf order is" statement(s). Using the PCF option will cause JED2VCL to produce HP PCF vectors which will greatly reduce the size of the VCL file.

VCL Vector Definition Section

JED2VCL produces the VCL Vector Definition section which defines all test vectors in Vector Control Language format.

If the PCF option is enabled, this section will not be created as it isn't required when using Pattern Capture Format vectors. By default, up to 2K vector definitions for the HP3065/AT and up to 8K for the HP3070/AT can be created. These vector definition limits are user-definable, which allows the user to specify a smaller limit for the older digital cards (1K vector definition limit) and a larger limit to take advantage of the vector compression techniques available on the HP3065AT and HP3070/AT testers. Each vector definition can be fully commented with the original .JWV file's test vector to provide readability. JED2VCL uses the "initialize to" statement to minimize the number of explicit "set" statements required by each vector definition and therefore reduces the size of the resultant .VCL file. To achieve the smallest possible .VCL file, the PCF option should be enabled.

VCL Vector Execution Section

JED2VCL produces the VCL Vector Execution section which contains a single execution unit which executes every defined vector. If the PCF option is enabled, the HP PCF statements are written between the "pcf" and "end pcf" statements within this execution unit.

To provide test support for those PLDs which are not initializable (toggle flip-flops without a set or clear, etc.), JED2VCL has a match mode option. If the JED2VCL match mode option is enabled, JED2VCL will generate a VCL "homingloop" block that will contain a user-definable number of execution statements. The "exit if pass" key word is placed after the last vector execution statement in the homingloop. The worst case and single pass "test time" is calculated and the proper number of piping statements are added when an uncounted homingloop is used with the vpx, vas, or vpu processor. This technique enables the tester to initialize the PLD into a "known" state so that it may be tested. By combining the match mode option with ATGEN software's aaseed key word, JED2VCL can automate the testing of many previously "untestable" PLD designs.

Translation Reports

A translation report is created by JED2VCL which includes all screen messages generated during a translation process. The report will contain information on the availability and necessity of single pin and multi-pin group disables. A list of initializable vectors is also included in the report.

Communication Interface

The .VCL files created by the JED2VCL software package can be transferred to the HP3065/HP3070 board testers using HP's Advanced Link software. The Advanced Link software insures fast, error-free VCL file transfers to and from your board tester. For those owners of the HP3070 series testers, Local Area Network (LAN) file transfers are possible by equipping your personal computer with the appropriate interface hardware and software. Please contact your local HP sales representative for more information on Advanced Link and Local Area Networks.

JED2VCL is written in "C" and is presently available for IBM PC/XT/AT personal computers and compatibles.

Technical Support Service and Updates

Technical support is provided under the support plan for your particular ATGEN base product.

ATGEN and ACUGEN are registered trademarks and AAACT, AALCA, AAMAX, AALAT, AAQL, SHARPEYE & FASTpass are trademarks of ACUGEN Software, Inc. All other trademarks are the property of their respective holders. 25jul96