JED2DTS is a software utility that translates the output of ACUGEN Software's ATGEN® test generator (the .JWV file) into a .DTS file for GenRad 227X and 228X in-circuit board testers. JED2DTS includes CKT2ACN, a utility that reads a GenRad .CKT file and derives PLD board topology constraints. When JED2DTS is used with ATGEN software, PLD test program development for GenRad 227X and 228X test systems is truly automated. JED2DTS is easy to use and will produce a .DTS file complete with DISABLE, INHIBIT, and FORCE sections!
Easy to Use
JED2DTS only requires the name of the .JWV file to generate a complete .DTS file. No knowledge of programming, or the board tester is needed. CKT2ACN requires the name of the .CKT file and the names of the PLDs to generate a .ACN file (board topology constraints) for each PLD on a circuit board. No knowledge of schematics, net lists, or circuit description files is needed.
Typically, JED2DTS translates a .JWV file into a complete .DTS file in under one minute. Typically, CKT2ACN creates .ACN files for all PLDs on a circuit board in under three minutes.
Automatic .ACN and Batch File Generation
CKT2ACN reads a .CKT file and creates a .ACN file for the specified PLDs. The .ACN files convey the PLD board topology constraints to the ATGEN software. CKT2ACN also produces a batch, command, or script file that runs the ATGEN software and JED2DTS on each PLD.
Optimum Disables, Inhibits, and Forces
JED2DTS utilizes the .CNN file (created by the ATGEN software) to produce minimal DISABLES, INHIBITS, and FORCES. Combinatorial outputs use only the pins required by their product terms. Registered outputs use the minimum number of pins possible in the HOLD statements. You have complete control over the algorithms used to select and construct the best digital guards possible.
Automatic Match Loop Generation
JED2DTS automatically creates a match loop wherever one is required, including the DISABLE, INHIBIT, and FORCE sections of the .DTS file. This feature provides seamless support for hard to initialize PLD designs. A match loop cycles the PLD into a known state regardless of its previous state. Sequential match loops are fully supported.
Automatic Match Loop Generation
JED2DTS automatically creates a match loop wherever one is required, including in the DISABLE, INHIBIT, FORCE sections of the .DTS file. This feature provides seamless support for hard to initialize PLD designs. A match loop cycles the PLD into a known state regardless of its previous state. Sequential match loops are fully supported.
Complete Test Program Generation
JED2DTS reads the .JWV file's vectors and produces all sections of the .DTS file. JED2DTS first creates the SIZE, INPUTS, OUTPUTS, TRI, and OPENE statements for the HEAD section. Next, the group, subgroup, and single pin DISABLE, INHIBIT, and FORCE (for BUSTEST) sections are created. JED2DTS then translates each of the .JWV file's vectors into DTS statements for the MAIN section of the .DTS file, ensuring that the PLD is tested to the fault coverage level reported by the ATGEN software. JED2DTS creates multiple bursts when required and can automatically switch to FAST burst mode if there are too many vectors (user-definable threshold) to test with non-SpeedPlus pins. Of course, you can customize JED2DTS to always generate FAST bursts for testers equipped with the high-speed driver option. Five different types of tri-state tests are supported and input-only tri-state pins are automatically excluded from the tri-state tests.
JED2DTS uses an auto-configuration file to determine how to generate a .DTS file. You can customize this file to your liking to establish the translation defaults. JED2DTS has over 80 user-definable features. To simplify the handling of special situations, the auto-configuration file settings can be temporarily altered from the command line.
JED2DTS produces a message file documenting the entire translation process. All critical data, including the translator settings, the command line, the fault coverage level, and the board topology constraints, are written directly into the .DTS file as comments for future reference. The .JWV file's vectors can also be included in the .DTS file as comments for cross reference--each vector is written as a comment immediately preceding the DTS statements associated with it.
JED2DTS for PC platforms includes communication software to provide error-free transfers to and from the tester. Communication software for Sun3, Sun4, SPARCstation, and VAX/VMS platforms is available upon request.
JED2DTS is available for IBM compatible PCs running PCDOS or MSDOS, Sun 3 workstations running SunOS 4.0.3 or later, Sun SPARCstations and Sun 4 workstations running SunOS 4.1.1 or later, and VAX/VMS.
Technical Support Service and Updates
Technical support is provided under the support plan for your particular ATGEN base product.