INSIDE:
Device supportSim models
Translators
This product catalog presents a general overview of all PLD ATG, Boundary Scan products available from ACUGEN Software, Inc.. Each product listing includes a brief description but for more detailed information refer to the specific Product Description for each product. These product descriptions are available at http://www.acugen.com and via fax and paper on request. When purchasing product from ACUGEN, users should contact an ACUGEN® sales person for current pricing, terms and conditions and licensing information.
ACUGEN Software has long led the market in test generation solutions for programmable devices and continues to support customers as they strive to meet newer challenges in testing these parts. If you want assistance in choosing the best configuration for your company's ATG needs please call us at (603) 261-2468 or email acugen@acugen today. Thanks for your interest in our ATGEN® product line.
......VECTOR GENERATORS and TESTABILITY ANALYZERS......
......VECTOR GENERATORS and TESTABILITY ANALYZERS......
S75 Hierarchial ATGEN Test Generator Full functional test generator, hierarchial vector sets, 5x faster than S55, four ATG algorithms, true min-max simulator, 1 million gate/10 million vector capacity, engine only. PLD, CPLD & FPGA device support purchased separately.
S55 Premium ATGEN Test Generator Full functional test generator, flat vector sets, four ATG algorithms, engine only. PLD, CPLD & FPGA device support purchased separately.
S25 FASTpass™ ATGEN Test Generator Fast, effective low-cost test generator, two ATG algorithms, engine only. PLD, CPLD & FPGA device support purchased separately.
S2020 SHARPEYE™ Testability Analyzer Analyzes digital logic designs and reports testability problem in easy-to-read format. Includes all JEDEC and FPGA models. Standalone.
ES2020 SHARPEYE Testability Analyzer Analyzes digital logic designs and reports testability problem in easy-to-read format. Add-on to ATGEN base product.
S34 PROGBSDL™ BSDL Customizer Modifies BSDL to match socket on board. Accepts manually specified customization instructions or will automatically extract the device footprint from FPGA design files. Standalone.
S36 TESTBSDL™ BSDL ATG Generates high coverage pin fault tests for boundary scan devices. Useful for BSDL verification and In-Circuit Board Test. Standalone. Translators to Verilog, VHDL, board testers and component testers are available but sold separately.
S37 MODBSDL™ BSDL Modeler Reads BSDL files to create an ACUGEN simulation model. Used in conjunction with model generators to produce simulation models for other simulators such as Verilog, HILO and LASAR. Simulation is beneficial for verification, board-level simulation, and fault grading. Standalone.
S38 AACDB™ Cluster Test ATG Reads board netlist and cluster definition in Victory format, generates vectors, fault grades, and produces a fault dictionary. Automates test and diagnostics generation for multidevice clusters for Victory users (including Acculogic, Asset Intertech, and Intellitech users). Requires S55 or S75 ATGEN package, models and vector translator.
S39 AASERVER™ Job Stream Manager Client/server enables sharing of an ATGEN installation over a network. Add-on to ATGEN base product.
S4 PROMATG™ Test Generator Generates tests for PROMs, EPROMs and EEPROMs. Standalone.
S5 AADELAY™ AC Test Generator Creates accurate timing for AC testing. Requires AC translator. Add-on to ATGEN base product.
JEDEC MODEL LIBRARIES
This section lists the models packages. For lists of models available for
individual purchase, see the Individual models section later in this document.
MSP3 Starter Library 98 JEDEC-based models up to 10 macrocell size. Includes models in MSP3 list.
6l16
MSP4 Intermediate Library 177 JEDEC-based models. Includes MSP3 models plus list in MSP4 chart.
mach4-32
ASP1 AMD/Vantis MACH Library All Vantis MACH device models presently on our price list plus ASP2. (30 models, covering MACH families 1, 2, 3, 4 and 5.) See ASP1 List.
mach4-192
ATM1PR Atmel Model Library (Premium) All Atmel device models presently on our price list. (8 models.) See ATM1PR List.
atm750
ATM1FP Atmel Model Library (Fast-Pass)
All Atmel device models presently on our price list.
(8 models.) See ATM1PR List.
CSP1PR Cypress Model Library (Premium) All Cypress device models presently on our price list. (19 models.) See CSP1PR Model List.
18g8
CSP1FP Cypress Model Library (Fast-Pass)
All Cypress device models presently on our price list.
(19 models.) See CSP1PR List.
MSP1 Deluxe Models Subscription
Includes all 221 JEDEC-based device models presently on our price
list plus MSP2. See MSP1 Table for list of models in MSP1 in addition to
those in MSP4.
aaqmax
MSP2 Deluxe Models Renewal Subscription to all JEDEC-based device models developed within the following four quarters. Requires MSP1 or MSP2 in prior year.
ASP2 AMD/Vantis MACH Renewal Subscription to all Vantis MACH models developed within the following four quarters. Requires ASP1 or ASP2 in prior year.
MP3FP FASTpass Deluxe Models FASTpass version of MSP1. Requires S25 base product.
MP2FP FASTpass MACH Models FASTpass version of ASP1. Requires S25 base product.
FPGA DEVICE SUPPORT
Actel Device Support
Reads .adl/.pin files produced by Actel's design software. Requires S25 or S55 or S75 base product. Choose one from list below.
ES6-AAACT-BACT1010, ACT1020, ACT1415, TI1010, TI1020, 40MX02.
ES8-AAACT-C ES6 plus1225, 1240, 1425, 1440, 40MX04, 42MX09.
ES9-AAACT-E ES8 plus1280, 1460, 3265, 42MX16, 54SX08.
ES32-AAACT-F ES9 plus14100, 32100, 32140, 42MX24, 54SX16.
ES43-AAACT-G ES32 plus32200, 32300, 54SX32.
ES40-AAACT-H ES43 plus32400, 42MX36, 42MX52, 54SX64.
ES55-AAACT-I ES43 plus54SX72.
ES16-AAACT-ZAll .adl/.pin files.
ES16-AAACT-Z-FPFASTpass version of ES16-AAACT-Z.
Altera MAX+PLUS II Device Support
Reads .rpt/.fit, and EDIF versions 2 and 3 netlists produced by Altera's MAX-PLUS II design system (use EDIF for accurate timing). Requires S25 or S55 or S75 base product. Choose one from list below.
ES2-AAMAX-32-AEPM5016, EPM5024, EPM5032, EPM7032, CY7C344.
ES3-AAMAX-128-B ES2 plus EPM5064, EPM5096, EPM5127, EPM5128, EPM5130, EPM7064, EPM7096, EPM7128, EPX880, CY7C342, CY7C343, CY7C346, EPS464.
ES7-AAMAX-256-C ES3 plus EPM5192, EPM7160, EPM7192, EPM7256, EPX8160, CY7C341.
ES20-AAMAX-512-E ES7 plus EPM7512, EPF8282, EPF8452, EPM9320.
ES22-AAMAX-F ES20 plus EPF8820, EPF8636, EPF81188, EPM9400, EPM9480, EPM9560, EPF10K10.
ES23-AAMAX-G ES22 plus EPF6016, EPF6024, EPF81500, EPF10K20, EPF10K30.
ES41-AAMAX-H ES23 plus EPF10K40, EPF10K50.
ES42-AAMAX-I ES41 plus EPF10K70, EPF10K100.
ES19-AAMAX-Z All .rpt/.fit and EDIF files produced by MAX-PLUS II.
ES19-AAMAX-Z-FPFASTpass version of ES19-AAMAX-Z.
Altera MAX Quartus Device Support
Reads .vo, .sdo and .pin files produced by Altera's Quartus design system and targeted to MAX devices.
Requires S25 or S55 or S75 base product. Choose one from list below.
ES62-AAQMAX-128-BEPM5016, EPM5024, EPM5032, EPM7032 EPM5064, EPM5096, EPM5127, EPM5128, EPM5130, EPM7064, EPM7096, EPM7128, EPX880.
ES63-AAQMAX-C ES62 plus EPM5192, EPM7160, EPM7192, EPM7256, EPX8160.
ES64-AAQMAX-E ES63 plus EPM7512, EPF8282, EPF8452, EPM9320.
ES65-AAQMAX-F ES64 plus EPF8820, EPF8636, EPF81188, EPM9400, EPM9480, EPM9560, EPF10K10.
ES66-AAQMAX-G ES65 plus EPF6016, EPF6024, EPF81500, EPF10K20, EPF10K30.
ES67-AAQMAX-H ES66 plus EPF10K40, EPF10K50.
ES68-AAQMAX-I ES67 plus EPF10K70, EPF10K100.
ES61-AAQMAX-Z All .vo/.pin files produced by Quartus for MAX devices.
ES61-AAQMAX-Z-FPFASTpass version of ES61-AAMAX-Z.
Lattice Device Support
Reads .sim netlist files produced by Lattice development system. Requires S25 or S55 or S75 base product. Choose one from list below.
ES14-AALAT-BpLSI1016, pLSI1024, pLSI1032, pLSI2032, pLSI2064, pLSI2096, pLSI2128, ispGDX80, ispGDX120.
ES15-AALAT-CES14 plus pLSI1048, pLSI1048C, ispLSI2192, pLSI3160, pLSI3192, ispGDX160, ispLSI5256.
ES31-AALAT-EES15 plus pLSI3256, pLSI3320, ispLSI5384, ispLSI5512.
ES56-AALAT-FES31 plus ispLSI8600, ispLSI8840.
ES57-AALAT-GES56 plus ispLSI81080.
ES58-AALAT-HES57 plus .
ES59-AALAT-IES58 plus .
ES17-AALAT-ZAll .sim files produced by Lattice pLSI design tools.
ES17-AALAT-Z-FPFASTpass version of ES17-AALAT-Z.
Lucent ORCA Device Support
Reads EDIF files produced by ORCA development system.
Requires S25 or S55 or S75 base product. Choose one from list below.
ES48-AAORCA-E 2c04, 2c06, 2c08, 2c04a, 2c06a, 2c08a, 2t04a, 2t06a, 2t08a.
ES49-AAORCA-F ES48 plus 2c10, 2c12, 2c15, 2c10a, 2c12a, 2c15a, 2t10a, 2t12a, 2t15a.
ES50-AAORCA-G ES49 plus 2c26, 2c26a, 2t26a, 3t20.
ES51-AAORCA-H ES50 plus 2c40, 2c40a, 2t40a, 3t30, 3c55, 3t55.
ES53-AAORCA-I ES51 plus 3c80, 3t80.
ES54-AAORCA-J ES53 plus 3t125.
ES52-AAORCA-Z All ORCA devices supported by ORCA development system.
ES52-AAORCA-Z-FP FASTpass version of ES52-AAORCA-Z.
QuickLogic Device Support
Reads EDIF netlist produced by QuickLogic's pASIC design tools.
Requires S25 or S55 or S75 base product. Choose one from list below.
ES26-AAQL-B 8x12B, CYP381, CYP382.
ES27-AAQL-C ES26 plus 12x16B, CYP383, CYP384.
ES28-AAQL-E ES27 plus 16x24B, CYP385, CYP386, 2003.
ES29-AAQL-F ES28 plus 24x32B, CYP388, 2005, 2007, 3012.
ES46-AAQL-G ES29 plus 2009, 2012, 2016, 3025, 3040.
ES47-AAQL-H ES46 plus 2020, 3060.
ES30-AAQL-Z All EDIF files produced by QuickLogic's pASIC
design tools.
ES30-AAQL-Z-FP FASTpass version of ES30-AAQL-Z.
Xilinx Device Support
Reads .xnf and .edn file produce by Xilinx XACT tools. Requires S25 or S55 or S75 base product.
Choose one from list below.
ES1-LCA2ICTany XC2000, XC3000, or XC4000 series LCA with
synthetic design.
ES10-AALCA-B ES1 plus XC2018, XC2064, XC3020, XC3120, XC4002, XC5202, XC7272, XC7336, XC7354, XC7372, XC9536, XC9572, XC95108.
ES11-AALCA-C ES10 plus XC3030, XC3042, XC3130, XC3142, XC4003, XC4004, XC5204, XC73108, XC73144, XC95144, XC95160, XC95180, XC95216, XCS05.
ES12-AALCA-D ES11 plus XC3064, XC3164, XC4005, XC4006, XCS10.
ES13-AALCA-E ES11 plus XC3064, XC3164, XC4005, XC4006, XCS10, XC3090, XC3190, XC4008, XC4010, XC5206, XC95288, XC95432, XCS20.
ES24-AALCA-F ES13 plus XC3195, XC4013, XC4020, XC5210, XC5215, XC95576, XCS30, XCS40.
ES25-AALCA-G ES24 plus XC4025, XC4028, XC4036.
ES45-AALCA-H ES25 plus XC4044, XC4052, XC4062, XCV50.
ES60-AALCA-I ES45 plus XC4085, XC40110, XC40150, XCV100, XCV150.
ES18-AALCA-Z All .xnf files and Xilinx EDIF files.
ES18-AALCA-Z-FP FASTpass version of ES18-AALCA-Z.
ES44-FPGA-OVERFP Oversized FASTpass For customers who have licensed one or more FPGA products below level Z, this option will allow larger devices to run, but in FASTpass mode. One of this option enhances all FPGA products otherwise licensed by customer.
Multi-FPGA Pricing Policy For installations that license multiple FPGA device support families, special multi-FPGA pricing is available.
BOARD TEST TRANSLATION SOFTWARE
TS1 JED2VCLTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into VCL or PCF format for HP3065/3070 in-circuit board testers, complete with disabling (digital guarding).
TS4 JED2DTSTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into DTS format for GenRad 227x/228x in-circuit board testers, complete with disabling (digital guarding).
TS15 JED2DTGLTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into DTGL format for GenRad 2750 in-circuit board testers, complete with disabling (digital guarding).
TS7 JED2S30Translates .jwv and .cnn files produced by ATGEN or TESTBSDL into .sr and .d files for Schlumberger/ Factron Series 30 in-circuit board testers, complete with disabling (digital guarding).
TS17 JED2MEDTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into Mediator format for Schlumberger 700 series in-circuit board testers, complete with disabling (digital guarding).
TS12 JED2L200Translates .jwv and .cnn files produced by ATGEN or TESTBSDL into .sym and .chr files for Teradyne L200/L300 families of in-circuit board testers, complete with disabling (digital guarding).
TS19 JED2ZDDTranslates .jwv files produced by ATGEN or TESTBSDL into Data Director format for Teradyne/ Zenthel Z800 in-circuit board testers.
TS20 JED2Z8KTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into vector template format for Z8000 in-circuit board testers, complete with disabling (digital guarding).
TS29 JED2Z18Translates .jwv and .cnn files produced by ATGEN or TESTBSDL into .asc vector template format for Teradyne Z1800 in-circuit board testers, complete with disabling (digital guarding). Also produces parallel vector format for Teradyne Victory cluster testing.
TS34 JED2SPECTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into .bdf vector template model format for Teradyne Spectrum in-circuit board testers, complete with PREFERRED-style disabling (digital guarding).
TS30 JED2LSMTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into LSM format for Marconi 80/53X in-circuit board testers, complete with disabling (digital guarding).
TS33 JED2TDLTranslates .jwv and .cnn files produced by ATGEN or TESTBSDL into TDL format for Marconi 4210 in-circuit board testers, complete with disabling (digital guarding).
COMPONENT TEST TRANSLATION SOFTWARE
TS2 JTLTranslates .jwv files produced by ATGEN or TESTBSDL software into LMI format for Sentry 7, 20, 21 component testers. Available only on Microsoft operating systems.
TS6 JTSTranslates .jwv and .jdl files produced by ATGEN or TESTBSDL software into complete functional plus DC test programs for Sentry 7, 20, 21 component testers.
TS14 JTS+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for Sentry 7, 20, 21 component testers. Requires AADELAY.
TS28 JED2S15Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for Sentry S15 and S50 component testers. Requires AADELAY.
TS35 JED283K+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for HP 83000 component testers. Requires AADELAY.
TS24 JED2HP82K+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for HP 82000 component testers. Requires AADELAY.
TS18 JED2MCT+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for MCT 2000 component testers. Requires AADELAY.
TS21 JED2TRIL+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for Trillium component testers. Requires AADELAY.
TS22 JED2ADV+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for Advantest component testers. Requires AADELAY.
TS25 JED2ANDO+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for ANDO component testers. Requires AADELAY.
TS16 JED2ATP+Translates .jdl files produced by AADELAY software into complete functional, DC and AC test programs for GenRad 115, 125, 130 component testers. Requires AADELAY.
TS27 JWV2ACTTranslates .jwv files produced by ATGEN software into Actel Activator programmer format.
SIMULATION TESTBENCH TRANSLATION SOFTWARE
TS37 JED2VTranslates .jwv files produced by ATGEN software into Verilog and VHDL test stimulus.
SIMULATOR MODEL GENERATORS
TS8 LASMOD LASARGenerates simulation models in Teradyne V6 LASAR structural model format with accurate timing. For ATGEN models, users can create new timing parameter files in order to model different speed grades of devices in the library. Requires at least one of ATGEN or MODBSDL products.
TS23 AAGHDL HILO Generates simulation models in GenRad HILO .cct format with accurate timing. For ATGEN models, users can create new timing parameter files in order to model different speed grades of devices in the library. Requires at least one of ATGEN or MODBSDL products.
TS36 ACUMOD VerilogGenerates simulation models in Verilog structural format with accurate timing. For ATGEN models, users can create new timing parameter files in order to model different speed grades of devices in the library. Requires at least one of ATGEN or MODBSDL products.
OTHER PRODUCTS This is a partial catalog. For a catalog covering other products, contact ACUGEN. Other products cover ATG for PLDs and FPGAs, AC Testing, PROM testing, and vector translation to a wide range of board and component testers.
TEST GENERATION SERVICE RUNS
ACUGEN can generate tests for designs as a service, with pricing depending on the size of the design. Customers wishing to out-source a large number of designs should call for volume pricing. For orders placed at single-quantity pricing, 50% of order will be available for software license purchase made within 90 days. Technical data required are: design netlist data (depends on manufacturer, call tech support if you need assistance), board level wiring constraint information if for board test, target tester type, fixture wiring data if for component test. In the event fault coverage is low, ACUGEN will return a testability report along with the test vectors.
INDIVIDUAL MODELS
The models available for individual purchase are listed below grouped by size/price category. The smallest size category is shown even though the MSP3 package is the most cost-effective way to acquire these models.
Size i JEDEC Models : 37512
Size h JEDEC Models : sm448 ,machv-512 ,37384
Size g JEDEC Models : mach4-384 ,mach4-512 ,machv-320 ,machv-384 ,37256
Size f JEDEC Models : machv-256 ,mach465 ,mach466 ,37192
Size e JEDEC Models : mach4-192 ,machv-192 ,atm5000 ,37128
mach4-96
mach4-64
mach4-32
6l16
ACUGEN and ATGEN are registered trademarks, and AADELAY, AASERVER, ACUFIX, ACUTAP, PROGBSDL, TESTBSDL and SHARPEYE are trademarks of Acugen Software, Inc. 30may02