Boundary Scan Products: Background Information

Backgrounder for ACUGEN Software, Inc. boundary scan products.

Boundary scan testing (aka JTAG and 1149.1) has been hailed for several years as the savior of board-level testing in this age of shrinking geometries and skyrocketing circuit complexity. Surprisingly, actual usage of boundary scan testing by major electronics manufacturers has lagged far behind the potential. Why?

ACUGEN’s research has identified several reasons for low utilization of boundary scan capability:

• Bugs in BSDLs. BSDL files formally define the structure and parameters of the boundary scan support circuitry inside a device, including the length of the scan chain and order of bits in the scan chain. BSDL files are provided free (i.e. unsupported) by manufacturers of boundary scan-capable devices. Many of these BSDLs have explicit quality disclaimers in them, typically saying that the BSDLs have never been tested.

• Lack of automation in some parts of the process, particularly in customizing BSDL files for programmable logic devices.

• Few, if any, boards are built entirely with boundary scan devices. This means the board has to be put on an in-circuit board tester to test the non-boundary scan devices. Once the board is on the in-circuit tester, it is usually easier to stick with the old known testing method (in-circuit) rather than go through the painful process of learning the new (boundary scan). This "stick to the old method" is particularly appealing in today’s fast-paced, down-sized, time-to-market-critical environment, but sacrifices the major long-term benefits of moving to boundary scan.

The major in-circuit board test suppliers, plus several other companies, currently provide boundary scan test development software products. These products go a long way toward automating and simplifying boundary scan test development, but they do not solve the above problems.

Companies that succeed in switching to boundary scan testing can achieve major savings and competitive advantages:

• By eliminating the need for in-circuit fixturing nails, circuit board densities can be increased. This allows more electronics in the same space or the same electronics in a smaller package. Many industries compete based on logic densities, e.g. hand-held communication and computing.

• Reducing the number and density of nails on in-circuit fixtures lowers costs and increases fixture reliability.

• Testing most of a board with boundary scan simplifies the requirements for testing the rest of the board, so a lower cost in-circuit or MDA system will suffice.


Boundary scan - test method, defined by IEEE std 1149.1, for testing electronic subassemblies, most notably circuit boards. Sometimes referred to as JTAG.

BSDL - Boundary Scan Description Language, defined in IEEE std 1149.1b, is the language for describing the boundary scan circuit elements inside a boundary scan-compliant device.

MDA - manufacturing defects analyzer, a type of low cost board tester that cannot run vectors but which can detect many of the more common board assembly defects.

ACUGEN Software, Inc. provides Automatic Test Generation solutions for user-configurable digital electronics: PLDs, FPGAs, gate arrays, boundary scan, and circuit boards through a worldwide distribution and support network. Visit us at

ACUGEN and ATGEN are registered trademarks and ACUTAP, PROGBSDL, TESTBSDL and MODBSDL are trademarks of ACUGEN Software, Inc.