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ACUMOD Software

ACUGEN[TM] Model Files into Verilog Format

ACUMOD[TM] software automatically converts ACUGEN Software's ATGEN[TM] model files into Verilog format simulation models. This product, when used in conjunction with ATGEN test generation software, allows conversion of raw PLD JEDEC files or FPGA netlists into VERILOG models.

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Great for Functional Board Test Simulations
Successful functional board test programs require mountains of diagnostic data (either for guided probe or fault dictionary). Whole-board Verilog simulation is one method for producing diagnostic data as part of a functional board test program. However, Verilog simulators need models for all devices on the board, which usually include a multitude of PLDs. Since every PLD design is different, users need to create a new model for each PLD design on the board.

Creating and verifying models is laborious and time consuming, so the most cost effective solution is to use our ACUMOD product to generate the models automatically from the JEDEC file. If the designer changes the design, just rerun the ACUMOD program --it is as simple as that!

Great for Design Verification
Sometimes a whole-board simulation is the best way to verify your design logic and check for unexpected device interactions. Here again, you need to have simulation models for all devices on the board, including the PLDs. This ACUMOD program automatically generates these models for Verilog simulators.

Accurate Timing Available
Accurate timing is most valuable in timing verification and applications that do guided probe diagnosis at clock-rate. The ACUMOD product includes timing data on thousands of PLDs, organized by PLD manufacturer order part numbers. Timing data includes primarily delay information, not pulse width, frequency, setup, hold and other margins. Some devices in our library do not have timing modeled -- timing can be added on request.

Requirements
ACUMOD software must be run on a computer that has an ATGEN base product installed. ACUMOD supports whatever models are installed with the ATGEN base product.

Related Products

Technical Support Service and Updates
Technical Support is provided under the support plan for your particular ATGEN base product.

Easy to Use
The translator is invoked by typing "ACUMOD" and operating a menu/fill-in-the-form interface that helps you choose the right device part numbers. For JEDEC-based models, customers can create new timing variants (i.e. new speed grade) by providing an ASCII file in an intuitive format.

A sample for a 22V10 is shown here: 

         /*
        * AmPALCE22V10
        * Source: AMD PAL Data Book 1990, 2-247
        * Commercial
        * 5-jan-91
        */
        tsu =  8.0e-9;
        tw  =  5.0e-9;
        twl =  5.0e-9;
        twh =  5.0e-9;
        tpd = 10.0e-9;
        tclk=  6.0e-9;  /* tCO */
        tco = 12.5e-9;
        tea = 10.0e-9;
        ter = 10.0e-9;
        tap = 15.0e-9;
        tar =  8.0e-9;
        fmax= 71.0e6;

Wide Range of PLD Types
ACUMOD supports all PLD types supported by ATGEN software. All popular FPGA families are supported based on netlists produced by their design tools as summarized in the table below:
Actel reads .adl, .pin, and .del files timing from .del
Altera MAX reads .edo or .rtp and .fit siming from .edo
Lattice ispLSI reads .sim timing from .sim
Lucent ORCA reads .edn no timing yet
QuickLogic reads .edo timing from .edo
Xilinx reads .edn no timing yet

FPGA netlist summary

The complete list of JEDEC-based models at the time this document was printed is:
mach4-192 ric16p8b 20ra10 26cv12 machv-192 mach465
mach4-32 ric16rp4b 20rp10 26v12 204e mach466
mach4-64 ric16rp6b 20rp4 29m16 mach210 473
mach4-96 ric16rp8b 20rp6 29ma16 mach211 501
5ac312 16rp4 20rp8 30s16 mach215 506
5ac324 16rp6 20rs10 32r16 mach220 507
6l16 16rp8 20rs4 32vx10 mach221 ep512
8l14 sig16v8 20rs8 42va12 mach230 machv-512
10h16p8 16v8 20s10 48n22 mach231 ep600
10h20eg8 16v8a 20v8 85c224 ep241 atm750
10h20ev8 16v8h 20v8a 85c22v10 253 atm750b
10h20p8 16vp8 20vp8 85c508 machv-256 780
10h8 16x4 20x10 100 273 839
10l8 16z8 20x4 103 ep310 ep900
12h6 18cv8 20x8 105 ep320 1016c4
12l10 18g8 20xrp10 mach110 machv-320 1016ld8
12l6 18l4 20xrp4 mach111 330 1016p4
14h4 18n8 20xrp6 mach120 331 1016rd8
14l4 18p8 20xrp8 m128 332 ep1200
14l8 18u8q 20xv10 machv-128 333 atm1500
16a4 18v10 22ap10 mach130 335 ep1800
16c1 18v8z 22cv10p mach131 371 atm2500
16h2 19l8 22cv10z m144 372 2552
16hd8 19r4 22p10 151 373 2605
16l2 19r6 22rx8a 153 374 2678
16l6 19r8 22v10 155 375 ph3032
16l8 20c1 22vp10 157 machv-384 ph3064
16ld8 20cg10 22xp10 159 405 ph3128
16n8 20g10 gaz23sv8 161 415 atm5000
16p8 20l10 23s8 162 mach435 6001
16pe8 20l2 24l10 163 mach436 6002
16r4 20l8 24r10 167 mach445 7024
16r6 20r4 24r4 168 mach446 9800
16r8 20r6 24r8 173 plx448
16ra8 20r8 24v10 179 sm448

All ACUGEN JEDEC-based models

ACUGEN and ATGEN are registered trademarks, and AADELAY, AASERVER, ACUFIX, ACUTAP, PROGBSDL, TESTBSDL and SHARPEYE are trademarks of Acugen Software, Inc.


21may99

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