AAQL software automatically converts qualified QuickLogic® designs into simulation models for use by ATGEN® test generation software. This preprocessor software product, when used in conjunction with ATGEN test generation software, allows vector generation for QuickLogic series programmable logic devices.
Great time saver when testing QuickLogic devices
QuickLogic devices (QL8X12, QL12X16,QL16X24,QL24X32 ...) are powerful and complex PLDs, best thought of as small gate arrays. Their flexibility and large size makes manual test development painful and time consuming. The AAQL and ATGEN software automate the test development process, thereby providing major time savings. ACUGEN® ATE translators are also available to produce component and in-circuit test programs, including automatic generation of digital guarding conditions for in-circuit board tests. We estimate the payback for AAQL software to be 1-4 testable QuickLogic designs.
Interface to Design
The AAQL translator reads the netlist information from a QuickLogic EDIF file (named .EDO) and writes out a .JED and a .MLB file. The .EDO file is generated by setting the backend simulation option to LMC from within the QuickLogic design tool.
Fault Classes
The AAQL translator produces models that support PINS, LOGIC and MIL454 fault classes. Fuse faults are not supported primarily because the .EDO files contain no fuse information.
Technical Support Service
Technical service and support, including upgrades, are provided in the same manner as your ATGEN base product.
Easy to Use
The translator is invoked by typing "AAQL", followed by the name of the design, at the operating system prompt.
FASTpass Version Available
For users wanting a fast and low-cost solution well suited to test for the following common board test defects: unprogrammed parts, part in backwards, wrong part/mislabeled part, catastrophic device failure, and numerous open pins, this product is tailored to shallow designs (sequential depth 10). It is a quick check only.
For those customers who need high coverage fault detection typical of our Premium ATGEN test generators, the Premium levels of pre-processors are the better choice.
Requirements
AAQL software must be run on a computer that has an ATGEN S25, S55 or S60 base product installed, and this base product must be maintained up to the latest revision at the time of initial AAQL purchase. The host computer should have at least 5MB of RAM to run QL8X12 designs and at least 16MB of RAM for QL24X32 designs.
You will need an S55 or S60 version of ATGEN software to run the Premium versions of this software, and an S25, S55 or S60 version to run the FASTpass versions.
.EDO files are obtained from the QuickLogic Seamless pASICR Design Environment (SpDE ), which is available from QuickLogic as part of their EDIF support tool product.
Success Rate for Premium Versions
Due to the potential complexity of QuickLogic devices no software can be guaranteed to reach high coverage on 100% of designs. We recommend that SHARPEYE testability analysis software be used during design to enhance testability. If SHARPEYE software is used and reports no problems with the testability items recommended by us, then we expect our success rate to be 90% on designs with fewer than 100 memory elements and 80% on designs with more than 100 memory elements. A 80% success rate means ATGEN software will detect 90% of detectable gate output stuck-at faults and 100% of pin stuck-at faults on 80% of a typical mix of designs. Note that even an 80% success rate will put you way ahead of writing all tests manually.
Our policy of requesting users to send us designs that attain low coverage has allowed us to make major improvements in our software over the past few years, and we expect the success rate on these QuickLogic devices to continue improving.
The testability items we recommend be checked are:
• sequential depth less than 500,
• no oscillators,
• no one-shots,
• no feedback-memories that interact with any other memories,
• all clocks, sets, resets controlled by external pins,
• no gated clocks,
• determinate initialization
• combinatorial tri-state enable control on outputs
PLEASE NOTE:
To test these devices the user must have access to a tester, or a programmer, with enough driver/sensors to stimulate & test all the pins of these devices.