AALAT software automatically converts qualified Lattice ispLSI TM (in-system programmable Large Scale Integration) & pLSI TM (programmable Large Scale Integration) designs into simulation models for use by ATGEN® test generation software. This preprocessor product, when used in conjunction with an ATGEN test generator, allows vector generation for high density programmable logic devices from Lattice Semiconductor Corporation.
Great time saver when testing Lattice pLSI or ispLSI devices.
Lattice pLSI & ispLSI devices are powerful and complex PLDs, best thought of as small gate arrays. Their flexibility and large size makes manual test development painful and time consuming. The AALAT and ATGEN software packages automate the test development process thereby providing major time savings. ACUGEN® ATE translators are available to produce component and in-circuit test programs including automatic generation of digital guarding conditions for in-circuit board tests. We estimate the payback for AALAT software to be 1-6 designs.
Interface to Design
The AALAT translator reads the netlist and pin numbering information from the .SIM file. The AALAT translator contains built-in support for all macros present in the Lattice design software. The .SIM file must be a flattened netlist generated by the Lattice .SIM file generator Version 1.5 or later.
The ACUGEN model representation models the logic inside each hard macro using the fewest possible ATGEN primitives (boolean gates, D-latch, tri-state gate, etc.).
The AALAT translator produces models that support PINS, LOGIC and MIL454 fault classes. Fuse faults are not supported primarily because the .SIM file contains no fuse information.
Technical Support Service
Technical service and support, including updates, are provided in the same manner as your ATGEN base product.
Easy to Use
The translator is invoked by typing "AALAT", followed by the name of the design, at the operating system prompt.
FASTpass Version Available
For users wanting a fast and low-cost solution well suited to test for the following common board test defects: unprogrammed parts, part in backwards, wrong part/mislabeled part, catastrophic device failure, and numerous open pins, this product is tailored to shallow designs (sequential depth 10). It is a quick check only.
For those customers who need high coverage fault detection typical of our Premium ATGEN test generators, the Premium levels of pre-processors are the better choice.
Requirements -- AALAT
AALAT software must be run on a computer that has an ATGEN S25, S55 or S60 base product installed, and this base product must be maintained up to the latest revision at the time of initial AALAT purchase. The host computer should have at least 6MB of RAM to run 1016 designs and at least 12MB of RAM for 1048 designs. These devices have critical CPU speed and memory requirements. See attached Memory Chart for recommendations.
You will need an S55 or S60 version of ATGEN software to run the Premium versions of this software, and an S25, S55 or S60 base product to run FASTpass versions.
.SIM files are obtained by running Version 2.5 of Lattice's PDS system, with the .SIM file generator program at least Version 1.5.
Success Rate for Premium Versions
Due to the potential complexity of Lattice pLSI and ispLSI devices no software can be guaranteed to reach high coverage on 100% of designs. We recommend that SHARPEYE testability analysis software be used during design to enhance testability. If SHARPEYE software is used and reports no problems with the testability items recommended by us, then we expect our success rate to be 90% on designs with fewer than 100 memory elements and 80% on designs with more than 100 memory elements. A 80% success rate means ATGEN software will detect 90% of detectable gate output stuck-at faults and 100% of pin stuck-at faults on 80% of a typical mix of designs. Note that even an 80% success rate will put you way ahead of writing all tests manually.
Our policy of requesting users to send us designs that attain low coverage has allowed us to make major improvements in our software over the past few years, and we expect the success rate on these Lattice devices to continue improving.
The testability items we recommend be checked are:
sequential depth less than 500,
no feedback-memories that interact with any other memories,
all clocks, sets, resets controlled by external pins,
no gated clocks,
combinatorial tri-state enable control on outputs
To test these devices the user must have access to a tester, or programmer with enough driver/sensors to stimulate & test all the pins of these devices.